1. The Field of the Invention
This invention relates to the field of integrated circuit manufacturing. In particular, this invention relates to adjusting design layouts to eliminate phase-shift conflicts for shifters on masks used to fabricate integrated circuits.
2. Description of Related Art
Conventional integrated circuit (IC) fabrication involves many steps in common with other processes that impose physical structures in a layer on a substrate, such as laying ink in patterns on a page, or laying chrome in patterns on a quartz substrate. Some of the important steps viewed at a high level are depicted in FIG. 1.
In step 110, engineers use a functional computer aided design (CAD) process, to create a schematic design, such as a schematic circuit design consisting of individual devices coupled together to perform a certain function or set of functions. The schematic design 115 is translated into a representation of the actual physical arrangement of materials upon completion, called a design layout 125, with a physical CAD process 120. If multiple layers are involved, as is typical for an IC, a design layout is produced for each layer, e.g., design layouts 125a, 125b, etc. FIG. 2 shows a sample design layout. A fabrication CAD process 130 produces one or more fabrication layouts 135, such as masks for each design layout 125a. The one or more fabrication layouts 135 are then used by a substantiation process 140 to actually produce physical features in a layer, called here the printed features layer 149.
One recent advance in optical lithography called phase shifting generates features in the printed features layer 149 that are smaller than the features on the mask 135a projected onto the printed features layer 149. Such fine features are generated by the destructive interference of light in adjacent separated windows in the mask called shifters. FIG. 3 shows two adjacent shifters, 310 and 312, in a mask 300. The shifters 310 and 312 are light transmissive areas on the mask separated by an opaque area 311 with a width of Wm 313 when projected onto the printed features layer 149. The projection of Wm onto the printed features layer 149 is limited by the resolution of the optical process. However, if the light of a single wavelength passing through one of the shifters, e.g. 310, is out of phase (by 180 degrees or xcfx80 radians) with the light of the same wavelength passing through the other shifter, e.g. 312, then an interference pattern is set up on the printed features layer 149 during the substantiation process 140. This interference generates a printed feature 350 having a width Wp 353 that is less than the width Wm 313 of the opaque area projected onto the printed features layer 149. In other embodiments, the width 313 and width 353 are much closer and can be equal. In each case, the width 353 of the printed feature is less than can be produced by the same optical system without phase shifting.
The use of phase shifting puts extra constraints on the fabrication layouts 135, and hence on the design layout, e.g. 125a. These constraints are due to several factors. One factor already illustrated is the need for finding space on the mask, e.g., 135a, for the two shifters, 310 and 312, as well as for the opaque area 311 between them. This precludes the one mask from placing additional features on the printed features layer 149 in the region covered by the projection of the two shifters 310 and 312 and the opaque area 311. Another factor is that overlapping or adjacent shifters on a single mask, used, for example, to generate neighboring phase-shifted features, generally do not have different phases. Adjacent shifters with different phases will produce a spurious feature.
Currently, design layouts 125 may provide the space needed for placement of phase shifters through design rules, but shifters are actually placed and simultaneously assigned a phase in the conventional fabrication design steps, not shown, in attempts to produce the fabrication layouts. As complex circuits are designed, such as by combining many standard cells of previously designed sub-circuits, shifters of different phases may overlap or become adjacent in the layouts, leading to phase-shift conflicts. It is generally recognized that resolving phase-shift conflicts should be done globally, after the whole circuit is laid out, because swapping the phases of a pair of shifters to resolve one conflict can generate a new conflict with another neighboring feature already located in the design or one added later. The conventional IC design systems try to reassign phases of individual pairs to resolve the conflicts at the end of the design process when all the phase conflicts are apparent. For example, iN-Phase(trademark) software from NUMERICAL TECHNOLOGIES, INC.(trademark) of San Jose, Calif., uses this conventional technique.
For example, FIG. 4 shows a T-junction element 440 that is desirably formed with narrow phase-shifted features 443, 442 and 444 as well as with wide non-critical features 441 and 445. FIG. 4A shows a pair of shifters 410 and 420 needed to form the vertical phase-shifted feature 443 of element 440. FIG. 4A also shows another shifter 415 disposed opposite shifter 410 to form the left half 442 of the horizontal phase-shifted feature of element 440. Similarly, FIG. 4A also shows a fourth shifter 425 disposed opposite shifter 420 to form the right half 444 of the horizontal phase-shifted feature of element 440. Shifters 415 and 425 are so close that they violate a design rule requiring at least a minimum spacing X between adjacent shifters. That is, separation 427 is less than X.
In the conventional fabrication CAD process, not shown, the shifters 410, 420, 415 and 425 are placed as shown and assigned phases, but the phase-shift conflict is not addressed until all the elements of the design layout have been accounted for. Then the design rule is applied in which shifters 415 and 425 are replaced by a single shifter 430.
However, there is no assignment of phase for shifter 430 that can simultaneously be opposite to the phases assigned to shifters 410 and 420, because shifters 410 and 420 are already opposite to each other. Thus such a design has a conflict that cannot be solved by changing the phases assigned to the shifters. Some re-arrangement of shifters or features or both is needed. In this example, however, the feature 440 from the physical design layout does not allow shifter 430 to be moved and does not allow another shifter to be inserted. Thus the fabrication CAD process 130 cannot move or change the shifters enough to resolve the conflict.
When a phase-shift conflict is irresolvable by the fabrication CAD process 130, then the physical CAD process 120 is run again to move or reshape the features, such as those of element 440. Process flow with an irreconcilable phase-shift conflict is represented in FIG. 1, which shows that fabrication layouts 135 are produced along the arrow marked xe2x80x9cSucceedxe2x80x9d if the fabrication CAD process 130 succeeds, but that control returns to the physical CAD process 120 along the arrow marked xe2x80x9cFailxe2x80x9d if the fabrication CAD process 130 fails, such as if it fails to resolve all phase conflicts.
While suitable for many purposes, the conventional techniques have some deficiencies. As designs, such as designs for IC circuits, become more complex, the time and effort involved in performing the physical CAD process 120 and the fabrication CAD process 130 increase dramatically, consuming hours and days. By resolving phase-shift conflicts at the end of this process, circumstances that lead to irresolvable phase-shift conflicts are not discovered until the end of these time consuming processes. The discovery of such irresolvable phase-shift conflicts induces the design engineers to start over at the physical CAD process 120. The processes 120 and 130 are repeated until final design layouts and fabrication layouts without phase-shift conflicts are produced. This procedure multiplies the number of days it takes a foundry to begin producing IC chips. In a commercial marketplace where IC advancements occur daily, such delays can cause significant loss of market share and revenue.
Techniques are needed to discover and resolve phase-shift conflicts earlier in the sequence of physical layout designing and fabrication layout designing. Repeatedly assigning phases to the same shifters is undesirable in such techniques, however, because such repetition indicates inefficient processing and wasted processing resources.
Techniques for forming a design layout with phase-shifted features, such as an integrated circuit layout, are described. The techniques include receiving information about a particular phase-shift conflict in a first physical design layout. The information indicates features that are logically associated with the particular phase-shift conflict. Then the first physical design layout is adjusted based on that information to produce a second design layout. By identifying potentially many features that are logically associated with the phase-shift conflict, many more options for adjusting the first physical design layout can be evaluated and a better overall solution to the phase conflict can be used. For example, the adjustment need not be made in the vicinity of the phase-shift conflict; but, instead, can be made in the vicinity of any of the logically associated features. One of these logically associated features may be more conveniently adjusted than the feature at the phase-shift conflict. For example, there may be more space in which to resolve a phase shift around the selected feature than is available around the feature where the phase conflict is first identified. For another example, the selected feature might be redesigned to be non-critical and therefore forego the use of shifters entirely. These techniques therefore may substantially simplify and reduce the costs of the redesign process in many circumstances.
In some embodiments, a phase-assignment graph is generated that logically associates the one or more features with the particular phase-shift conflict. In some embodiments, the adjusting is performed on the first physical design layout to a selected feature of the one or more features. In some embodiments the adjusting step involves changing the selected feature to a non-critical feature that does not use phase shifting. In some embodiments, the adjusting involves reverse compaction to consolidate empty space for the second design layout. In some embodiments, multiple potential solutions to a phase conflict are generated based on the logically associated features, the solutions are evaluated, and the solution providing a most favorable value is picked.